Development of Verification and Emulation Environments for complex Chiplet Designs
Development of UVM-SV Scoreboards for self-checking regressions
Development of Functional Coverage as part of Metric Driven Verification Environments
Development of SystemVerilog Assertions for use in Formal and Simulation Environments
Development of Emulation Environments based on Cadences Palladium Emulator Product
Integration of Cadence Verification IP (VIP) for Simulation Environments
Integration of Accelerated VIP (AVIP) for Emulation Environments
Definition and Management of Verification Plans (vPlans) using Cadence vManager tools
Creation and Management of Automated Regression Environments, e.g. Jenkins, GIT
Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001
Close Collaboration with Architects and Design Engineers to debug complex test scenarios

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
10+ years' experience in microelectronics/EDA industry
Experience of Verilog RTL Design essential
Experience of Metric Driven Verification (MDV) essential
Experience of Formal Verification Methodologies essential
Excellent oral and written English essential
Self-motivated with excellent planning, interpersonal, and communication skills
Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred
Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

1 Cadence Design Systems, Inc. jobs in Scotland